MT48LC4M32B2P-7:G DRAM Memory ICs LM135AH N87C51FA Semiconductors
Features
- PC100-compliant
- Fully synchronous; all signals registered on positive edge of system clock
- Internal pipelined operation; column address can be changed every clock cycle
- Internal banks for hiding row access/precharge
- Programmable burst lengths: 1, 2, 4, 8, or full page
- Auto precharge, includes concurrent auto precharge and auto refresh modes
- Self refresh mode (not available on AT devices)
- Auto refresh
– 64ms, 4096-cycle refresh (commercial and industrial)
– 16ms, 4096-cycle refresh (automotive)
- LVTTL-compatible inputs and outputs
- Single 3.3V ±0.3V power supply
- Supports CAS latency (CL) of 1, 2, and 3
| DRAM |
| SDRAM |
| 5.4 ns |
| 3.6 V |
| 3 V |
| 165 mA |
| 0 C |
| + 70 C |
| Product Type: | DRAM |
| Subcategory: | Memory & Data Storage |
